By Zeidman B.
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Extra info for Introduction to CPLD and FPGA Design
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Using these signals to reset state machines frees up interconnect for other uses. Asynchronous reset should be used only for resetting the entire chip and should not occur during normal functioning of the chip. After reset, you must ensure that the chip is in a stable state such that no flip-flops will change until an input changes. You must also ensure that the inputs to the chip are stable and will not change for at least one clock cycle after the reset is removed. 2 Asynchronous latches on inputs Some buses, such as the VME bus, are designed to be asynchronous.
By repeating the same pseudorandom series of bits, the resulting signature should be the same for each chip. Any chip that produces an incorrect signature is a bad chip. This type of testing is probabilistic and assumes that a pseudo-random sequence of events has a good chance of catching errors, which may not be true. However, it requires very little hardware to implement and can be used as a simple form of BIST. 7. SIMULATION ISSUES Perhaps the most important phase of chip design, and the most often overlooked phase, is that of simulation.
While not all of these techniques need to be included in your design, those that are needed should be included at design time. DFT techniques should be taken into account during the design process rather than afterwards. Otherwise, circuits can be designed that are later found to be difficult, if not impossible, to test. One important consideration that can be overlooked, is that test logic is intended to increase the testability and reliability of your chip. If test logic becomes too large, it can actually decrease reliability because the test logic can itself have problems which cause the chip to malfunction.