By Prabhat Mishra
Validation of programmable architectures, together with processor cores, coprocessors, and reminiscence subsystems, is likely one of the significant bottlenecks in present System-on-Chip layout technique. A severe problem in validation of such structures is the shortcoming of a golden reference version. for that reason, many current validation thoughts hire a bottom-up method of layout verification, the place the performance of an latest structure is, in essence, reverse-engineered from its implementation. conventional validation suggestions hire diversified reference types counting on the abstraction point and verification job, leading to capability inconsistencies among a number of reference models.This publication provides a top-down validation technique that enhances the present bottom-up ways. It leverages the method architect's wisdom in regards to the habit of the layout via structure specification utilizing an structure Description Language (ADL). The authors additionally handle basic demanding situations in sensible verification: loss of a golden reference version, and shortage of a accomplished useful insurance metric.Functional Verification of Programmable Embedded Architectures: A Top-Down strategy is designed for college kids, researchers, CAD instrument builders, designers, and bosses drawn to the improvement of instruments, recommendations and methodologies for system-level layout, microprocessor validation, layout house exploration and practical verification of embedded structures.
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The opcode list in each unit is a sorted list. Architecture-specific Properties The architecture must be well-formed based on the original intent of the architecture model. Here we mention some of the architecture specific properties we verify in our framework. D The number of operations processed per cycle by a unit can not be smaller than the total number of operations sent by its parents unless the unit has a reservation station. , killing no operation (NOP). • The instruction template should match the available pipeline bandwidth.
VALIDATION OF STATIC BEHAVIOR 35 Algorithm 1: Verify Connectedness Inputs: i. Graph model of the architecture G ii. ListOfUnits: list of units in the graph G iii. ListOfStorages: list of storages in the graph G Outputs: i. True, if the graph model satisfies this property else false. ii. In case of failure, report the disconnected components. Begin Unmark all the entries in all the input lists. InsertQ(root, Q) /* Put root node of G in queue Q */ while Q is not empty Node n = DeleteQ(0 /* Remove the front element of Q */ Mark n as visited in G case type of node n unit: Mark n in ListOfUnits storage: Mark n in ListOfStorages endcase for each successor node s of n Us is not visited InsertQ(s, Q) endfor endwhile Return true if all the entries are marked in all of the input lists; false otherwise, and report the unmarked components.
The argument-to-storage (storage-to-argument) mapping is a bi-directional function that maps argument nodes in the behavior to storage nodes in the structure. For example, the argument-storage mappings for the ADD operation are mappings from {DEST, SRCI, SRC2} to RegisterFile. 34 CHAPTER 3. VALIDATION OF SPECIFICATION Each functional unit (with read or write ports) supports certain data-transfer operations. These operations can be derived from the above mapping functions. 2 supports register read (regRead) for ADD and LD opcodes; the MEM unit supports data read (dataRead) and data write (dataWrite) from LI data cache; the Fetch unit supports instruction read (instRead) from LI instruction cache; the WriteBack unit supports register write (regWrite).