By Zhuo Ma, Zhenyu Zhao, Yang Guo, Lunguo Xie, Jinshan Yu (auth.), Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang (eds.)
This booklet constitutes the refereed court cases of the sixteenth nationwide convention on laptop Engineering and know-how, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers provided have been conscientiously reviewed and chosen from 108 submissions. they're prepared in topical sections named: microprocessor and implementation; layout of integration circuit; I/O interconnect; and dimension, verification, and others.
Read Online or Download Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers PDF
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Additional resources for Computer Engineering and Technology: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers
And Qlink is used in combination with SDP to deal with data communication among DSP cores, Keypoints are transferred by QLink when it is suitable for bulk data transmission, and the number of keypoints and data synchronization signals are transferred by SDP when it is suitable for light and fast data transmission. The method we have presented can fully develop multi-level parallelism of YHFT-QDSP architecture, and accelerate the speed of parallel SURF algorithm. The parallel SURF algorithm is fully tested using 5 different image samples for scale change, rotation, change in illumination, addition of noise and affine transformation.
In order to conceal memory access latency, different stream processors use different methods. For example, VIRAM puts DRAM into the chip, Imagine[1-2] and Merrimac adopt multilevel memory structure. We design a 64-bit programmable stream processor FT64(Fei Teng 64), which aims at exploiting the parallelism and locality of the applications in domains of signal processing, multimedia and scientific computing. FT64 inherits some characteristics of other stream processors, such as stream programming model and multilevel memory structure.
Rapid object detection using a boosted cascade of simple features. In: IEEE Conference on Computer Vision and Pattern Recognition, pp. : Boxlets: a fast convolution algorithm for signal processing and neural networks. cn Abstract. Stream architecture is a newly developed high performance processor architecture oriented to multimedia processing. FT64 is 64-bit programmable stream processor and it aims at exploiting the parallelism and locality of the applications. In this paper, first, we inspect the memory access characteristics of FT64 with cache and without cache.