By Keliu Shu, Edgar Sanchez-Sinencio
This e-book provides either basics and the state-of-the-art of PLL synthesizer layout and research recommendations. an entire review of either system-level and circuit-level layout and research are coated. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is carried out in 0.35m m CMOS. It contains a high-speed and strong phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which take on velocity and integration bottlenecks of PLL synthesizer elegantly. This publication is conceived as a PLL synthesizer handbook for either academia researchers and layout engineers.
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2001 J. McNeill, “A simple method for relating time- and frequency-domain measures of oscillator performance,” in Proc. SSMSD’2001, Feb. 2001, pp. 7-12 U. Moon, K. Mayaram, and J. Stonick, “Spectral analysis of time-domain phase jitter measurements,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 321-327, May 2002 A. Zanchi, A. Bonfanti, S. Levantino, and C. Samori, “General SSCR vs. cycle-to-cycle jitter relationship with application to phase noise in PLL,” in Proc. SSMSD’2001, Feb. 2001, pp. 32-37 J.
Circuits Syst. II, vol. 49, pp. 321-327, May 2002 A. Zanchi, A. Bonfanti, S. Levantino, and C. Samori, “General SSCR vs. cycle-to-cycle jitter relationship with application to phase noise in PLL,” in Proc. SSMSD’2001, Feb. 2001, pp. 32-37 J. Yang, S. Kim, S. Kim, and B. Jeon, “Fast switching frequency synthesizer using direct analog techniques for phase-array radar,” Radar 97, Oct. 1997, pp. 386-390 A. Rokita, “Direct analog synthesis modules for an X-band frequency source,” International Conference on Microwaves and Radar, vol.
In [11], the PLL sampling delay due to discrete-time operation of PFD is modeled as the PFD update period However, the sampling delay is exaggerated in [11]. As shown in Fig. 3-10, the PFD operation is the impulse sampling, not the sample-and-hold. An accurate result of the stability limit based on linearized approximate difference equations was derived in [1], and it agrees well with the Matlab behavioral modeling in the Appendix. Chapter 3 44 Figure 3-10. 3 Locking time Considering that the PLL is initially locked and the frequency divide ratio changes due to channel switching, we calculate the locking time for a given frequency error.